The adoption of chiplet technology provides additional security risks, such as easing the production of counterfeit goods. Chiplet technology incentivizes designers to source chiplets from around the globe, increasing the potential for a supplier to distribute faulty goods. In this document, we extensively explore a power delivery network (PDN) fingerprinting methodology which specifically targets chiplet technology to protect consumers from receiving counterfeit devices. The authentication method we developed targets chiplet Field Programmable Gate Arrays (FPGAs). Moreover, we successfully implemented and tested our design with physical measurement. The ultimate goal of this work is to accurately and precisely track voltage fluctuations in FPGAs through physical measurement in order to authenticate a chiplet System on Chip (SoC); a chiplet SoC comprises individual chiplets, the interposer, and the connections between them. In our threat assessment and final analysis, we show how this authentication technology is able to detect and reject untrustworthy chiplets. Our fingerprinting method extracts valuable information from the PDN in a chiplet system. The PDN is a power supply network shared by all loads in chiplet architectures, and any significant changes in one chiplet will cause changes in the PDN, which can be measured in another chiplet through the shared PDN. Moreover, The usage of voltage transients to fingerprint a chiplet system is a novel approach that is also able to create consistent and unique fingerprints. In our project, we create voltage transients by energizing large loads in a short time span, and use sensors colocated in the same authenticating chiplet to trace the voltage levels. Fingerprinting is a useful tactic that can impede or prohibit an adversary from producing and distributing counterfeit chiplets, and in order to source chiplets from untrusted sources, the chiplet system must be authenticated as a whole. In our design, we energize and subsequently de-energize a large load using ring oscillators (ROs) in a unique pattern as a challenge. We then measure the resulting voltage transient or response using time to digital converters (TDCs). TDCs are are built on-chip, out of generaic FPGA resources, and measure voltage with high resolution and a high time sampling rate on the order of 10s of μV and approximately 2ns respectively. We show that the transient response from energizing or de-energizing a large load is inherently unique to a chiplet SoC, and metrics can be extracted and used to fingerprint a chiplet system. The challenge and response combination is hidden from the adversary to prevent them from mimicking the unique signature. In our work, we tested different chiplet systems, and verified the effectiveness of the fingerprinting method when there are minor alterations to a trusted design. In our analysis, we’ve determined optimal fingerprinting strategies by implementing several different configurations of measurement devices, such as TDCs which can rapidly measure PDN voltage. The results obtained are used to determine optimal quantity, type, combinations, and floor plan locations of components in the authentication chiplet, such as power wasters and a voltage sensor device using the Virtex UltraScale+ VCU118 FPGA development kit, designed to measuring PDN transients for fingerprinting purposes. We show that through the use of the L1 and L2 distance norms for signal analysis, our fingerprinting device can detect power changes to PDN at a 2mW resolution, or approximately two thousand active ring oscillators, which is less than 1% of the available logic resources in a VCU118 chiplet.